Design and Implementation of Area and Power Optimized High Speed Multipliers

[1]. Jasmine Nessa, S. Dash, and M. C. Tripathy, “High Speed Low Power 16×16 Dadda Multiplier by Utilizing Reversible Gates,” 2025 IEEE
5th International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI SATA), 2025
[2]. S. Ramkumar and Harish M. Kittur, "Low Power and Area Efficient Carry Select Adder," IEEE Transactions on Very Large-Scale
Integration Systems, vol. 20, no. 2, pp. 371–375, 2012.
[3]. L. Dadda, "Some Schemes for Parallel Multipliers," Alta Frequenza, vol. 34, pp. 349–356, 1965.
[4]. C. S. Wallace, "A Suggestion for a Fast Multiplier," IEEE Transactions on Electronic Computers, vol. EC-13, no. 1, pp. 14–17, 1964.
[5]. N. H. E. Weste and D. Harris, CMOS VLSI Design: A Circuits and Systems Perspective, 4th Edition, Pearson Education, 2011.
[6]. M. Morris Mano, Digital Design, 5th Edition, Pearson Education, 2013.
[7]. John F. Wakerly, Digital Design Principles and Practices, 4th Edition, Pearson Education, 2008.
[8]. Xilinx Inc., Vivado Design Suite User Guide, 2020.
[9]. Douglas Perry, VHDL Programming by Example, McGraw Hill Publications.
[10]. Rabaey Jan M., Digital Integrated Circuits: A Design Perspective, Pearson Education.
[11]. Behrooz Parhami, Computer Arithmetic: Algorithms and Hardware Designs, Oxford University Press.
[12]. I. Koren, Computer Arithmetic Algorithms, 2nd Edition, A.K. Peters Ltd., 2001.
[13]. D. A. Patterson and J. L. Hennessy, Computer Organization and Design: The Hardware/Software Interface, 5th Edition, Morgan Kaufmann
Publishers, 2014.
[14]. S. Knowles, “A Family of Adders,” Proceedings of the 14th IEEE Symposium on Computer Arithmetic, pp. 277–281, 1999.
[15]. A. Weinberger and J. L. Smith, “A Logic for High-Speed Addition,” National Bureau of Standards Circular, vol. 591, pp. 3–12, 1958.
[16]. K. Hwang, Computer Arithmetic: Principles, Architecture and Design, John Wiley & Sons, 1979.
[17]. R. P. Brent and H. T. Kung, “A Regular Layout for Parallel Adders,” IEEE Transactions on Computers, vol. C-31, no. 3, pp. 260–264,
1982.
[18]. B. Parhami, “Efficient VLSI Algorithms for Parallel Multiplication,” IEEE Transactions on Computers, vol. 38, no. 6, pp. 880–887, 1989.
[19]. S. Hauck and A. DeHon, Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation, Morgan Kaufmann
Publishers, 2008.
[20]. Stephen Brown and Zvonko Vranesic, Fundamentals of Digital Logic with Verilog Design, 3rd Edition, McGraw-Hill Education, 2014.