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Design and Implementation of Area and Power Optimized High Speed Multipliers
1 2 3 4 5 Department of Electronics and Communication Engineering, BGS Institute of Technology, Adichunchanagiri University, Karnataka, India.
Published Online: May-August 2026
Pages: 05-13
Cite this article
↗ https://www.doi.org/10.59256/indjece.20260302001
Multipliers are one of the most essential arithmetic components used in digital systems such as digital signal processing, communication systems, processors, image processing, and embedded applications. The overall performance of these systems mainly depends on the speed, power consumption, and area utilization of the multiplier architecture. Conventional multipliers suffer from high delay, increased power consumption, and larger hardware complexity, which affects system efficiency. To overcome these limitations, a high-speed and power optimized 16×16 Dadda-style multiplier is proposed and implemented using Verilog HDL. The proposed design generates partial products using conventional logic and reduces them efficiently using a tree-based reduction structure inspired by the Dadda multiplication technique. To further improve system performance, pipelining is introduced using input and output registers, which helps in reducing critical path delay and improving timing efficiency. The design is implemented and verified on FPGA using Vivado, and its performance is analysed in terms of power, delay, and area utilization. The obtained results show reduced power consumption, improved speed, and efficient hardware utilization, making the proposed multiplier suitable for real-time digital and embedded applications.
