Design and Implementation of Area and Power Optimized High Speed Multipliers

Lakshmi J S; Dr. Manoj Kumar S B; Keerthi G S; Tejas B S; Naveen K B

doi:10.59256/indjece.20260302001

Original Article

Design and Implementation of Area and Power Optimized High Speed Multipliers

Paper ID 40
Volume 3, Issue 2
Pages: 05-13
Published Online: May-August 2026
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Authors

Lakshmi J S¹
Dr. Manoj Kumar S B²
Keerthi G S³
Tejas B S⁴
Naveen K B⁵

¹ ² ³ ⁴ ⁵ Department of Electronics and Communication Engineering, BGS Institute of Technology, Adichunchanagiri University, Karnataka, India.

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Article Information

DOI: https://www.doi.org/10.59256/indjece.20260302001
Published In: Year 2026 · Volume 3 · Issue 2
Published Online: May-August 2026
Pages: 05-13
Article Type: Original Article
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Citations

Lakshmi J S, Dr. Manoj Kumar S B, Keerthi G S, Tejas B S, Naveen K B, “Design and Implementation of Area and Power Optimized High Speed Multipliers”, Indian Journal of Electronics and Communication Engineering, Volume 03, Issue 02, May-August 2026, PP: 05-13.

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Design and Implementation of Area and Power Optimized High Speed Multipliers

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