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Low-Power Artificial Neural Network Implementation on Artix 7 FPGA Using Reversible Logic
1 M. Tech, VLSI System Design, CVR College of Engineering, Hyderabad, Telangana, India. 2 3 B Tech, Department of ECE, Scient Institute of Technology, Hyderabad, Telangana, India.
Published Online: January-April 2025
Pages: 21-26
This paper presents an energy-efficient hardware implementation of an Artificial Neural Network (ANN) using reversible logic gates. The proposed ANN design is implemented in Verilog HDL and tested on various FPGA platforms, including Zynq-7000, Virtex-7, Kintex-7, and Artix-7. The novelty of this work lies in leveraging reversible logic gates, such as the Peres gate, to construct fundamental arithmetic units like half adders, full adders, a 4-bit ripple carry adder (RCA), and a 4-bit array multiplier, ultimately forming the neuron structure. The power consumption analysis across different FPGA architectures highlights the efficiency of the proposed approach, with Artix-7 achieving the lowest power consumption at 0.077W. The results demonstrate significant power savings compared to conventional ANN implementations, making this design suitable for low-power AI/ML Applications.
