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VLSI Technologies for Next-Generation Consumer Electronics: Trends and Design Perspectives
Authors
1 Department of ECE, K S Institute of Technology, Bangalore, Karnataka, India.
Article Information
- Published In
- Year 2025 · Volume 2 · Issue 3
- Published Online
- September-December 2025
- Pages
- 01-02
- Article Type
- Original Article
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References
1. Sangiovanni-Vincentelli and G. Martin, “Platform-based design and software design methodology for embedded systems,” IEEE Design & Test of Computers, vol. 18, no. 6, pp. 23–33, 2006.
2. A. B. Kahng and B. Li, “VLSI physical design: From planar to 3D ICs,” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 39, no. 11, pp. 3127–3140, 2020.
3. W. Wolf, Modern VLSI Design: IP-Based Design, Prentice Hall, 2010.
4. T. Chen, T. Krishna, J. Emer, and V. Sze, “Eyeriss: A spatial architecture for energy-efficient dataflow for convolutional neural networks,” IEEE Micro, vol. 36, no. 3, pp. 92–108, 2018.
5. P. Duraisamy and T. Sinharoy, “Advances in FinFET and GAAFET technologies for next-generation processors,” IEEE Trans. Electron Devices, vol. 70, no. 5, pp. 2301–2314, 2023.
6. J. L. Hennessy and D. A. Patterson, Computer Architecture: A Quantitative Approach, 6th ed. Morgan Kaufmann, 2019.
7. V. Narang and S. Gupta, “Design considerations for low-power IoT SoCs: Trends and challenges,” Microelectronics Journal, vol. 114, p. 105146, 2021.
8. X. Li and Y. Zhou, “Trends in 3D integration and heterogeneous packaging for consumer electronics,” J. Semicond. Technol. Sci., vol. 22, no. 4, pp. 321–334, 2022.
9. Y. Zhang and J. Wang, “AI-enabled VLSI design automation for next-generation electronics,” IEEE Access, vol. 11, pp. 45890– 45904, 2023.
10. R. Singh and A. Kumar, “Low-power VLSI design techniques for portable electronics: A review,” Int. J. Electron. Commun., vol. 110, p. 152889, 2020.
2. A. B. Kahng and B. Li, “VLSI physical design: From planar to 3D ICs,” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 39, no. 11, pp. 3127–3140, 2020.
3. W. Wolf, Modern VLSI Design: IP-Based Design, Prentice Hall, 2010.
4. T. Chen, T. Krishna, J. Emer, and V. Sze, “Eyeriss: A spatial architecture for energy-efficient dataflow for convolutional neural networks,” IEEE Micro, vol. 36, no. 3, pp. 92–108, 2018.
5. P. Duraisamy and T. Sinharoy, “Advances in FinFET and GAAFET technologies for next-generation processors,” IEEE Trans. Electron Devices, vol. 70, no. 5, pp. 2301–2314, 2023.
6. J. L. Hennessy and D. A. Patterson, Computer Architecture: A Quantitative Approach, 6th ed. Morgan Kaufmann, 2019.
7. V. Narang and S. Gupta, “Design considerations for low-power IoT SoCs: Trends and challenges,” Microelectronics Journal, vol. 114, p. 105146, 2021.
8. X. Li and Y. Zhou, “Trends in 3D integration and heterogeneous packaging for consumer electronics,” J. Semicond. Technol. Sci., vol. 22, no. 4, pp. 321–334, 2022.
9. Y. Zhang and J. Wang, “AI-enabled VLSI design automation for next-generation electronics,” IEEE Access, vol. 11, pp. 45890– 45904, 2023.
10. R. Singh and A. Kumar, “Low-power VLSI design techniques for portable electronics: A review,” Int. J. Electron. Commun., vol. 110, p. 152889, 2020.
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