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- Vol. 1 Issue 3
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Design and Implementation of a High-Speed Non-Overlapping Mealy Sequence Detector for Digital Communication
Authors
1 M. Tech I-Year, VLSI System Design, CVR College of Engineering, Hyderabad, Telangana, India. 2 B. Tech III-Year, ECE, Scient Institute of Technology, Hyderabad, Telangana, India
Article Information
- DOI
- No Doi
- Published In
- Year 2024 · Volume 1 · Issue 3
- Published Online
- September-December 2024
- Pages
- 01-05
- Article Type
- Original Article
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