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An Intelligent Irrigation Control System Using IoT
Authors
1 Assistant professor, Department of Electronics and Communication Engineering, Lords Institute of Engineering and Technology, Hyderabad, Telangana, India. 2 3 4 5 Students, Department of Electronics and Communication Engineering, Lords Institute of Engineering and Technology, Hyderabad, Telangana, India.
Article Information
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- No Doi
- Published In
- Year 2025 · Volume 2 · Issue 1
- Published Online
- January-April 2025
- Pages
- 13-20
- Article Type
- Original Article
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References
1. International Journal of Recent Trends in Engineering & Research (IJRTER) Volume 03, Issue 03; March - 2017 [ISSN: 2455-1457]
2. J. Cong, M. Huang, and Y. Zou, "Accelerating Deep Neural Networks with Specialized Hardware," IEEE Transactions on Computer-Aided
Design of Integrated Circuits and Systems, vol. 37, no. 8, pp. 1510-1521, Aug. 2018. doi: 10.1109/TCAD.2018.2808810.
3. N. Domala and G. Sasikala. “Low power flipped voltage follower current mirror with improved input output impedances.”. Sadhana, 46:1–
11, 2021. DOI: https://doi.org/10.1007/s10470-023-02205-4..
4. N. Jouppi et al., "In-Datacenter Performance Analysis of a Tensor Processing Unit," Proceedings of the 44th Annual International
Symposium on Computer Architecture (ISCA), Toronto, ON, 2017, pp. 1-12. doi: 10.1145/3079856.3080246.
5. S. Han, H. Mao, and W. J. Dally, "Deep Compression: Compressing Deep Neural Networks with Pruning, Trained Quantization and Huffman
Coding," International Conference on Learning Representations (ICLR), San Juan, Puerto Rico, May 2016. [Online]. Available:
https://arxiv.org/abs/1510.00149.
6. D. Shin, J. Park, and M. Pedram, "A Power-Aware Neural Network Training System Using Dynamic Voltage Scaling," IEEE Transactions
on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 4, pp. 1153-1162, April 2017. doi: 10.1109/TVLSI.2016.2633988.
7. A. Krizhevsky, I. Sutskever, and G. E. Hinton, "ImageNet Classification with Deep Convolutional Neural Networks," Communications of the
ACM, vol. 60, no. 6, pp. 84-90, 2017. doi: 10.1145/3065386.
8. N. Domala, G. Sasikala, and N. Raj.Low volt-age high bandwidth FVF current mirror using quasifloating self-cascode output
stage.Analog In-teg. Circ. Signal Process,:1–13,2023 DOIhttps://doi.org/10.1007/s10470-023-02205-4
9. S. Liang, Y. Du, S. Song, and H. Shen, "Low-Power and High-Throughput VLSI Architecture for Neural Network Processing," IEEE
Transactions on Signal Processing, vol. 68, pp. 2306-2316, May 2020. doi: 10.1109/TSP.2020.2974728.
10. C. Zhang et al., "Optimizing FPGA-Based Accelerator Design for Deep Convolutional Neural Networks," Proceedings of the 2015
ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Monterey, CA, USA, 2015, pp. 161-170. doi:
10.1145/2684746.2689060.
11. N. Domala and G. Sasikala.Low voltagequasi floating gate current mirror with im-proved output impedance.Int. J. Public
Sec-tor Perform. Manag,10:499–512, 2022.DOI: 10.1504/IJPSPM.2022.126404
12. N. Raj, A.K. Singh, and A.K. Gupta. Low power highoutput impedance high bandwidth QFGMOS currentmirror.Microelectron. J,45:1132–
1142, 2014. DOI https://doi.org/10.1016/j.mejo.2014.05.005
13. N.Domala, Gsasikala, A Low Input Impedance Wide Bandwidth Flipped Voltage Follower Current Mirror, Indian Journal of Engineering
& Materials Sciences Vol. 30, August 2023, pp. 622-628 DOI: 10.56042/ijems.v30i4.365.
14. P. A. Kumar, S. Tamil, and N. Raj. “Low voltage improved impedance wide bandwidth current mirror.”. International Journal of Information
Technology, 13:2411–2417, 2021. DOI: https://doi.org/10.1007/s41870-021-00785-w.
2. J. Cong, M. Huang, and Y. Zou, "Accelerating Deep Neural Networks with Specialized Hardware," IEEE Transactions on Computer-Aided
Design of Integrated Circuits and Systems, vol. 37, no. 8, pp. 1510-1521, Aug. 2018. doi: 10.1109/TCAD.2018.2808810.
3. N. Domala and G. Sasikala. “Low power flipped voltage follower current mirror with improved input output impedances.”. Sadhana, 46:1–
11, 2021. DOI: https://doi.org/10.1007/s10470-023-02205-4..
4. N. Jouppi et al., "In-Datacenter Performance Analysis of a Tensor Processing Unit," Proceedings of the 44th Annual International
Symposium on Computer Architecture (ISCA), Toronto, ON, 2017, pp. 1-12. doi: 10.1145/3079856.3080246.
5. S. Han, H. Mao, and W. J. Dally, "Deep Compression: Compressing Deep Neural Networks with Pruning, Trained Quantization and Huffman
Coding," International Conference on Learning Representations (ICLR), San Juan, Puerto Rico, May 2016. [Online]. Available:
https://arxiv.org/abs/1510.00149.
6. D. Shin, J. Park, and M. Pedram, "A Power-Aware Neural Network Training System Using Dynamic Voltage Scaling," IEEE Transactions
on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 4, pp. 1153-1162, April 2017. doi: 10.1109/TVLSI.2016.2633988.
7. A. Krizhevsky, I. Sutskever, and G. E. Hinton, "ImageNet Classification with Deep Convolutional Neural Networks," Communications of the
ACM, vol. 60, no. 6, pp. 84-90, 2017. doi: 10.1145/3065386.
8. N. Domala, G. Sasikala, and N. Raj.Low volt-age high bandwidth FVF current mirror using quasifloating self-cascode output
stage.Analog In-teg. Circ. Signal Process,:1–13,2023 DOIhttps://doi.org/10.1007/s10470-023-02205-4
9. S. Liang, Y. Du, S. Song, and H. Shen, "Low-Power and High-Throughput VLSI Architecture for Neural Network Processing," IEEE
Transactions on Signal Processing, vol. 68, pp. 2306-2316, May 2020. doi: 10.1109/TSP.2020.2974728.
10. C. Zhang et al., "Optimizing FPGA-Based Accelerator Design for Deep Convolutional Neural Networks," Proceedings of the 2015
ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Monterey, CA, USA, 2015, pp. 161-170. doi:
10.1145/2684746.2689060.
11. N. Domala and G. Sasikala.Low voltagequasi floating gate current mirror with im-proved output impedance.Int. J. Public
Sec-tor Perform. Manag,10:499–512, 2022.DOI: 10.1504/IJPSPM.2022.126404
12. N. Raj, A.K. Singh, and A.K. Gupta. Low power highoutput impedance high bandwidth QFGMOS currentmirror.Microelectron. J,45:1132–
1142, 2014. DOI https://doi.org/10.1016/j.mejo.2014.05.005
13. N.Domala, Gsasikala, A Low Input Impedance Wide Bandwidth Flipped Voltage Follower Current Mirror, Indian Journal of Engineering
& Materials Sciences Vol. 30, August 2023, pp. 622-628 DOI: 10.56042/ijems.v30i4.365.
14. P. A. Kumar, S. Tamil, and N. Raj. “Low voltage improved impedance wide bandwidth current mirror.”. International Journal of Information
Technology, 13:2411–2417, 2021. DOI: https://doi.org/10.1007/s41870-021-00785-w.
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